Field of the Invention
The present invention relates to a method and a configuration for generating a clock pulse in a data processing system having a number of data channels.
Data processing systems with a number of independent data channels, particularly integrated switching networks (ICs) are problematic since the individual channels can have different data rates as a result of different clock pulse frequencies given the transmission of data on the different data channels. In the corresponding standards, two hundred ppm usually is the maximum allowed deviation of the different data rates or, respectively, clock pulse frequencies. Due to the described problem, it is not possible to simultaneously process a number of independent channels, in a data processing system, with only one clock pulse without additional measures.
In order to solve the explained problem, a configuration is known wherein, for each data channel, a required system clock pulse is acquired on a basis of a phase-locked loop (PLL) circuit from the data of the respective data channel or from a co-supplied clock pulse. A PLL circuit has a voltage-controlled oscillator (VCO) providing the desired clock pulse. PLL circuits are known in the prior art and, therefore, are not described in greater detail.
The configuration has the disadvantage that a PLL circuit is necessary for each data channel to be sampled in order to realize a signal sampling of a number of independent channels having different data rates. Therefore, a number of voltage-controlled oscillators (VCO) must be disadvantageously used. In addition to the costs associated therewith, there is the danger that the voltage-controlled oscillators or, respectively, PLL circuits disturb each other as a result of coupling processes and thus generate an undesired jitter in the system.
As an alternative to the use of a PLL circuit, the use of a delay-locked loop (DLL) is known from the prior art, which generates an output signal having a predetermined delay vis-á-vis an input reference signal. For example, U.S. Pat. No. 5,614,855, Published, European Patent Application No. EP 0 349 715 A2 and U.S. Pat. No. 5,317,288 describe DLL circuits. The article by T. H. Lee, K. S. Donnelly, J. T. C. Ho, J. Zerbe, M. G. Johnson, C. Eshikawa: titled “A 2.5 V CMOS Delay-Locked Loop for 18 Mbit, 500 Megabyte/s DRAM”, IEEE-Journal of Solid-State Sircoits, vol. 29, No. 12, December 1994, pages 1491 to 1496 describes a DLL circuit having an infinite delay range or, respectively, dynamic range. Therefore, the DLL circuit can arbitrarily delay an output signal in its phase. As a result, the phase difference between two channels can be continuously adapted.